1. Field of the invention
The present invention relates to a semiconductor memory, and more specifically to a synchronous DRAM (dynamic random access memory) having a plurality of banks constituting a memory cell array and a function of selecting a bank to be read, written and precharged, from the plurality of banks.
2. Description of Related Art
In a semiconductor memory operating at a high speed, which is generally called a synchronous DRAM, performance is evaluated on the basis of the amount of data which can be read and written in a constant time. Therefore, in order to eliminate a loss time which corresponds to a precharging time of the memory cell array inherent to the DRAM and which also corresponds to a gap occurring between continuous data inputtings/outputtings, it is a conventional practice to divide the memory cell array into some number of groups and to provide one control circuit for each of the groups independently of the other groups to the effect that the groups of the memory cell array are alternatively read and written. Thus, the loss time in the data inputtings/outputtings can be equivalently eliminated. Ordinarily, each of the groups obtained by dividing the memory cell array is called a "memory bank" or simply a "bank". A synchronous DRAM having 2.sup.N banks (where N is positive integer), typified by 2 banks, 4 banks, or 8 banks, has been already developed. In the following, each of the groups of the memory cell array will be called simply a "bank". The number of banks depends upon a demand in an application, and in the prior art, a circuit construction has been adopted which can selectively operate with different bank number structures (for example, a 2-bank structure and a 4-bank structure) in a chip of the same design, so as to meet with a demand of a different bank number.
Now, one prior art example of the synchronous DRAM, which can selectively operate with either 2-bank structure or a 4-bank structure, will be described with reference to the drawings.
First, operation of the prior art example in the 4-bank structure will be described. In the following, a data reading operation will be described, but explanation of a data writing operation will be omitted for simplification of description, since a bank selection operation and a bank activation operation in the data writing operation are the same as those of the data reading operation.
Referring to FIG. 1, there is shown a block diagram of the prior art example of the synchronous DRAM. As shown in FIG. 1, the prior art synchronous DRAM includes a bank control signal generating unit 600 receiving a pair of bank selection signals 200 and 201, a RAS (row address strobe) command signal 240, a CAS (column address strobe) command signal 241, a WE (write enable) command signal 242 and a CS (chip select) command signal 243 (which are called an "active command signal"), and a predetermined bank switching signal 248, and for generating an internal activation command signal 205, an internal read/write command signal 207, bank activation signals 220, 221, 222 and 223 and read/write bank selection signals 224, 225, 226 and 227. The shown synchronous DRAM also includes an address signal generating unit 102 receiving address signals Ai (i=1, 2, . . . , n) (bus 244), and for generating internal row address signals Xi (bus 245) and internal column address signals Yi (bus 246), and a memory cell array 101 receiving the signals outputted from the bank control signal generating unit 600 and the address signal generating unit 102, for supplying and receiving a read/write data through a data input/output unit 103.
Referring to FIG. 2, the memory cell array 101 is divided into four banks 700, 701, 702 and 703 each including a group of memory cells and a control circuit associated therewith. Each of the four banks 700, 701, 702 and 703 is coupled to receive the internal row address signals Xi, 245 and the internal column address signals Yi, 246, and is connected to an input/output data bus 704, which is connected to the input input/output unit 103, for the purpose of outputting the read data and receiving data to be written. In addition, the bank 700 receives the bank activation signal 220 and the read/write bank selection signal 224, and the bank 701 receives the bank activation signal 221 and the read/write bank selection signal 225. The bank 702 receives the bank activation signal 222 and the read/write bank selection signal 226, and the bank 703 receives the bank activation signal 223 and the read/write bank selection signal 227.
Referring to FIG. 3, there is shown a block diagram illustrating a portion of an internal construction of each of the banks 700, 701, 702 and 703. The banks 700, 701, 702 and 703 have the same construction and operate in the same manner. The shown bank includes a latch signal generating circuit 822 receiving the corresponding bank activation signal 220-223, decode circuit blocks 800, 801 and 802 each including an AND gate receiving the internal row address signals Xi (bus 245), and a D-latch circuit 805 having a data input D connected to an output of the AND gate 832 and a gate control input G connected to an output of the latch signal generating circuit 822.
The shown bank also includes a row decode circuit 803 having a word line driver (AND circuit) 806 receiving an output of the decode circuit blocks 800, 801 and 802 through internal row address bus lines 804 and the corresponding bank activation signal 220-223, a word line 807 connected to an output of the word line driver 807, a memory cell 808 included in the memory cell array of the corresponding bank and connected to the word line 807 and a digit line 809, and a sense amplifier 811 connected between a pair of complementary digit lines 809 and 810 and enabled by the corresponding bank activation signal 220-223.
The shown bank furthermore includes a column decode circuit 812 having a column switch driver (AND circuit) 813 receiving the internal column address signals Yi (bus 246) and the corresponding read/write bank selection signal 224-227, and a column switch circuit 814 composed of MOS transistors 815, 816, 817 and 818 connected as shown. The MOS transistors 815 and 816 are connected in series between one of a pair of complementary reading bus lines 819 and 820 and ground, and the MOS transistors 817 and 818 are connected in series between the other reading bus line 820 and ground. A gate of the MOS transistors 815 and 817 are connected in common to an output of the column switch driver 813. A gate of the MOS transistors 816 and 818 are connected to the pair of complementary digit lines 809 and 810, respectively. The pair of complementary reading bus lines 819 and 820 are connected to a pair of complementary inputs of a data amplifier circuit 821 enabled by the corresponding read/write bank selection signals 224-227 and having an output connected to the input/output data line 704. As well known to persons skilled in the art, actually, a number of memory cells are arranged to form a memory cell matrix having a number of rows and a number of columns. Therefore, a number of word lines and a number of digit lines are actually provided, so that, there are provided the decode circuit blocks of the corresponding number, the word line drivers of the corresponding number, the sense amplifiers of the corresponding number, the column switch drivers of the corresponding number, the column switches of the corresponding number and the data amplifiers of the corresponding number. However, for simplification of the drawings, only the decode circuit blocks 800, 801 and 802, one word line 807, one memory cell 808, the pair of digit lines 809 and 810, one sense amplifier 811, one column switch driver 813, one column switch 814, and one data amplifier 821 are shown in FIG. 3. In addition, since an internal construction and an operation of each of the decode circuit blocks 801 and 802 are the same as that of the decode circuit block 800, the internal construction of each of the decode circuit blocks 801 and 802 is omitted in FIG. 3 for simplification of drawing.
Referring to FIG. 4, there is shown a block diagram illustrating an internal construction of the bank control signal generating unit 600. The shown bank control signal generating unit 600 includes clocked buffer circuits 212, 213, 214 and 215 receiving the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243, respectively, and controlled in common by an internal clock signal 230, a command decode circuit 204 receiving an output of the clocked buffer circuits 212, 213, 214 and 215, for generating the internal activation command signal 205, an internal precharge signal 206 and the internal read/write command signal 207, and clocked buffer circuits 210 and 211 receiving the bank selection signals 200 and 201, respectively, and controlled in common by the internal clock signal 230 for generating internal bank selection signals 208 and 209, respectively.
The shown bank control signal generating unit 600 also includes a bank activation signal generating circuitry 900 receiving the internal bank selection signals 208 and 209, the bank switching signal 248 supplied from an external, the internal activation command signal 205, and the internal precharge signal 206, for generating the bank activation signals 220, 221, 222 and 223 for the four banks 700, 701, 702 and 703, respectively, and a 1 5 read/write bank selection signal generating circuitry 901 receiving the bank activation signals 220, 221, 222 and 223, the internal bank selection signals 208 and 209, the internal read/write command signal 207, and the bank switching signal 248, for generating the bank selection signals 224, 225, 226 and 227 for the four banks 700, 701, 702 and 703, respectively.
Referring to FIG. 5, there is shown a timing chart illustrating an operation of the synchronous DRAM in the 4-bank structure. The synchronous DRAM operates completely in synchronism with a clock signal, and an input signal is latched and internally fetched in synchronism with a rising edge of the clock signal. The operation of the synchronous DRAM is determined by a combination of the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243. In the timing chart of FIG. 5, "ACT" at a timing T1 is determined by a specific logical value combination of the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243, which are called the active commands. This active command "ACT" corresponds to a falling of the RAS command signal 240 in a conventional DRAM, and in response to this active command, the address signals Ai, 244 and the bank selection signals 200 and 201 are fetched, so that the activation signal for the bank selected by the bank selection signals 200 and 201 is generated, and a corresponding memory cell is activated. The bank selection signals are used for select a bank to be selected. In the 4-bank structure, therefore, one bank is selected by a logical value combination of two bits (corresponding to the bank selection signals 200 and 201). In this case, when both of the logical values of the bank selection signals 200 and 201 are at a logical low level, the bank 700 is selected, and when the logical values of the bank selection signals 200 and 201 are at a logical high level and at the logical low level, respectively, the bank 701 is selected. When the logical values of the bank selection signals 200 and 201 are at the logical low level and at the logical high level, respectively, the bank 702 is selected, and when both of the logical values of the bank selection signals 200 and 201 are at the logical high level, the bank 703 is selected.
In the circuit of FIG. 4, the bank selection signals 200 and 201 are latched in the buffer circuits 210 and 211 in response to the internal clock signal 230, and are outputted as the internal bank selection signals 208 and 209 to the bank activation signal generating circuitry 900 and the read/write bank selection signal generating circuitry 901. At the timing T1 shown in FIG. 5, both the internal bank selection signals 208 and 209 are outputted at the logical low level corresponding to the logical low level of the bank selection signals 200 and 201. On the other hand, the active command signals including the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243, are supplied through the buffer circuits 212, 213, 214 and 215 to the command decode circuit 204, and decoded to generate the internal activation command signal 205, the internal precharge signal 206 and the internal read/write command signal 207. The internal activation command signal 205 and the internal precharge signal 206 are supplied to the bank activation signal generating circuitry 900, and the internal read/write command signal 207 is supplied to the read/write bank selection signal generating circuitry 901. In this case, the internal activation command signal 205 outputted from the command decode circuit 204 in response to the active command signals is brought into the logical high level.
Referring to FIGS. 6A, 6B, 6C and 6D, there are shown examples of an internal construction of the bank activation signal generating circuitry 900 of the prior art constructed to be able to operate in the 4-bank structure. The bank activation signal generating circuitry 900 includes four, namely, first, second, third and fourth bank activation signal generating circuits shown in FIGS. 6A, 6B, 6C and 6D, respectively, for generating the bank activation signals 220, 221, 222 and 223 for the banks 700, 701, 702 and 703, respectively.
The first bank activation signal generating circuit shown in FIG. 6A for generating the bank activation signal 220, includes inverters 1003, 1005 and 1025, a NAND gate 1006, AND gates 1000 and 1001, and NOR gates 1002 and 1004, which are connected as shown. The second bank activation signal generating circuit shown in FIG. 6B for generating the bank activation signal 221, includes inverters 1010 and 1026, a NAND gate 1012, AND gates 1007 and 1008, and NOR gates 1009 and 1011, which are connected as shown. The third bank activation signal generating circuit shown in FIG. 6C for generating the bank activation signal 222, includes inverters 1016, 1018 and 1027, a NAND gate 1028, AND gates 1013 and 1014, and NOR gates 1015 and 1017, which are connected as shown. The fourth bank activation signal generating circuit shown in FIG. 6D for generating the bank activation signal 223, includes inverters 1022 and 1029, a NAND gate 1030, AND gates 1019 and 1020 and NOR gates 1021 and 1023, which are connected as shown.
At the timing T1 shown in FIG. 5, both the logical low level of the bank selection signals 200 and 201 supplied to the bank control signal generating unit 600 are both at the logical low level, and therefore, both the internal bank selection signals 208 and 209 are also at the logical low level. Therefore, the bank 700 is selected as mentioned hereinbefore. In the 4-bank structure operation, on the other hand, the bank switching signal 248 of the logical high level is supplied from the external to the first bank activation signal generating circuit shown in FIG. 6A for the bank 700. Here, it is a conventional practice that the bank switching signal 248 is fixed to either the logical high level or the logical low level in a product manufacturing process. In addition, the internal precharge command signal 206 is set to the logical low level.
Now, assume that all the bank activation signals 220, 221, 222 and 223 outputted from the bank activation signal generating circuits are initially at the logical low level. In the first bank activation signal generating circuit shown in FIG. 6A, if the internal activation command signal 205 is brought to the high level at the timing T1, since both the internal bank selection signals 208 and 209 are at the logical low level, an output of the AND gate 1000 is brought to the logical high level, and an output of the NOR gate 1002 is brought to the logical low level, so that an output of the inverter 1003 is brought to the logical high level, with the result that the bank activation signal 220 is brought to the logical high level. On the other hand, since the internal precharge command signal 206 is at the logical low level, an output of the AND gate 1001 is at the logical low level. As mentioned above, since the output of the NOR gate 1002 is at the logical low level, an output of the NOR gate 1004 is brought to the logical high level. Therefore, the output of the NOR gate 1002 is maintained at the logical high level, regardless of the output level of the AND gate 1000. Thus, the bank activation signal 220 is maintained at the logical high level.
At a rising of the clock signal in a timing T2 shown in FIG. 5, the active command signals including the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243, are supplied through the buffer circuits 212, 213, 214 and 215 to the command decode circuit 204 and the internal activation command signal 205 outputted from the command decode circuit 204 is brought to the logical low level. Accordingly, the output of the AND gate 1000 is brought to the logical low level.
On the other hand, the address signal generating unit 102 receiving the address signals Ai, 244, fetches the address signal in response to the internal activation command signal 205 of the logical high level at the timing T1 shown in FIG. 5, and outputs the internal row address signal Xi, 245 to the memory cell array 101. The row address value indicated by the internal row address signal Xi, 245 corresponding to the address signals Ai, 244, at the timing T1 is shown as "ROW1" in FIG. 5.
Here, the address signal generating unit 102 comprises a clocked buffer circuit 216 and D-latch circuits 501 and 502, connected as shown in FIG. 7. The address signal Ai, 244 is supplied through the buffer circuit 216 controlled by the clock signal 230, to a data input D of each of the D-latch circuits 501 and 502. In response to the internal activation command signal 205 supplied to a gate control input G of the D-latch circuit 501, the address signal Ai, 244 is fetched in the D-latch circuit 501, which in turn outputs the internal row address signal Xi, 245. On the other hand, in response to the internal read/write command signal 207 supplied to a gate control input G of the D-latch circuit 502, the address signal Ai, 244 is fetched in the D-latch circuit 502, which in turn outputs the internal column address signal Yi, 246.
The clocked buffer circuit 210 to 215 shown in FIG. 4 and the clocked buffer circuit 216 shown in FIG. 7 are constructed as shown in FIG. 8. Namely, the clocked buffer circuit includes an input signal receiver circuit 1200 receiving an input signal, and a D-type flipflop circuit 1201 having a data input D connected to an output of the input signal receiver circuit 1200 and a clock input C connected to receive the internal clock signal 230. Thus, the input signal is supplied through the input signal receiver circuit 1200 to the D-type flipflop circuit 1201 and is latched in the D-type flipflop circuit 1201 in synchronism with the internal clock signal 230, so that the latched signal is outputted from an output Q of the D-type flipflop circuit 1201.
The bank activation signal 220 outputted from the first bank activation signal generating circuit shown in FIG. 6A and the internal row address signal Xi, 245 supplied from the address signal generating unit 102, are supplied to the bank 700, as shown in FIG. 2. The bank activation signal 220 is supplied to the latch signal generating circuit 822 shown in the block diagram of FIG. 3 illustrating the internal construction of each bank. At a transition of the logical low level to the logical high level of the bank activation signal 220, a latch signal 822A is generated in the latch signal generating circuit 822, and supplied to the gate control input G of the D-latch circuit 805 included in each of the decode circuit blocks 800, 801 and 802.
On the other hand, the internal row address signals Xi, 245 are supplied to the AND gate 832 included in each of the decode circuit blocks 800, 801 and 802, and a logical product output of the AND gate 832 is supplied to the data input D of the D-latch 805. Thus, in each of the decode circuit blocks 800, 801 and 802, a first stage of a decoding processing for the internal row address signals Xi, 245 is executed, and the internal row address signals Xi, 245 are latched in response to the latch signal 822A generated in the latch signal generating circuit 822. The internal row address signals Xi, 245 decoded in the decode circuit blocks 800, 801 and 802, are supplied to the row decode circuit 803.
In this row decode circuit 803, the word line driver 806 brings to the logical high level the word line 807 selected by the bank activation signal 220 and the internal row address signals Xi, 245. The sense amplifier 811 is also activated in response to the bank activation signal 220. Thus, data read from the memory cell 808 to the digit lines 809 and 810 because the word line 807 has been brought to the logical high level, is amplified by the sense amplifier 811.
At a timing T3 in the timing chart of FIG. 5, the active command signals including the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243, are supplied through the buffer circuits 212, 213, 214 and 215 to the command decode circuit 204. In addition, in response to the bank selection signal 200 of the logical low level and the bank selection signal 201 of the logical high level, the internal bank selection signal 208 of the logical low level and the internal bank selection signal 209 of the logical high level are supplied to the bank activation signal generating circuitry 900 and the read/write bank selection signal generating circuitry 901.
As mentioned hereinbefore, when the internal bank selection signals 208 and 209 are at the logical low level and at the logical high level, respectively, the bank 702 is selected and activated. If the internal activation command signal 205 supplied to the bank activation signal generating circuitry 900 shown in FIG. 4 is at the logical high level, an output of the AND gate 1013 in the third bank activation signal generating circuit shown in FIG. 6C for the bank 702, is brought to the logical high level. Therefore, an output of the NOR gate 1015 is brought to the logical low level, so that an output of the inverter 1016 is brought to the logical high level, with the result that the bank activation signal 222 is brought to the logical high level. On the other hand, since the internal precharge command signal 206 is at the logical low level, an output of the AND gate 1014 is at the logical low level. As mentioned above, since the output of the NOR gate 1015 is at the logical low level, an output of the NOR gate 1017 is brought to the logical high level. Therefore, the output of the NOR gate 1015 is maintained at the logical low level, regardless of the output level of the AND gate 1013. Thus, the bank activation signal 220 is maintained at the logical high level.
At the same time, as shown in the timing chart of FIG. 5, since the row address value "ROW2" is supplied as the internal row address signal Xi, 245, the word line 807 corresponding to the row address value "ROW2" is selected, and data of the memory cell 808 is amplified by the associated sense amplifier 811.
At a rising of the clock signal in a timing T4 shown in FIG. 5, the external active command signals are supplied through the buffer circuits 212, 213, 214 and 215 to the command decode circuit 204 and decoded by the command decode circuit 204 so that the internal activation command signal 205 is brought to the logical low level. Accordingly, at this timing, the output of the AND gate 1013 in the third bank activation signal generating circuit shown in FIG. 6C is brought to the logical low level.
What is shown as "RED" at a timing T6 in the timing chart of FIG. 5, is one called a read command, which is recognized by a specific logical value combination of the external active command signals including the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243. The read command is one corresponding to a falling of the CAS command signal 241 in a conventional DRAM, and in response to this active command, the address signals Ai, 244 and the bank selection signals 200 and 201 are fetched, so that the read/write bank selection signal for the bank selected by the bank selection signals is generated, and data is read out from a column address corresponding to the address signal.
At a timing T6 in the timing chart of FIG. 5, the active command signals including the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243, are supplied through the buffer circuits 212, 213, 214 and 215 to the command decode circuit 204, and decoded by the command decode circuit 204 to bring the internal read/write command signal 207 to the logical high level. Since the bank activation signals 220 and 222 outputted from the bank activation signal generating circuitry 900 at this timing T6 are at the logical high level, the bank 700 and 702 are in the activated condition. Therefore, the banks which can be read at this situation are only the banks 700 and 702. Since both the bank selection signals 200 and 201 have been brought to the logical low level at the timing T6, the bank 700 is selected. The bank selection signals 200 and 201 of the logical low level are outputted through the buffer circuits 210 and 211 as the internal bank selection signals 208 and 209 of the logical low level, respectively, and supplied to the read/write bank selection signal generating circuitry 901.
Referring to FIGS. 9A, 9B, 9C and 9D, there are shown examples of an internal construction of the read/write bank selection signal generating circuitry 901 of the prior art constructed to be able to operate in the 4-bank structure. The read/write bank selection signal generating circuitry 901 includes four, namely, first, second, third and fourth read/write bank selection signal generating circuits shown in FIGS. 9A, 9B, 9C and 9D, respectively, for generating the bank selection signals 224, 225, 226 and 227 for the banks 700, 701, 702 and 703, respectively.
The first read/write bank selection signal generating circuit shown in FIG. 9A for generating the bank selection signal 224, includes a NAND gate 1101, an AND gate 1102, a D-latch circuit 1103 and an inverter 1104, connected as shown. The second read/write bank selection signal generating circuit shown in FIG. 9B for generating the bank selection signal 225, includes a NAND gate 1110, an AND gate 1111, and a D-latch circuit 1112, connected as shown. The third read/write bank selection signal generating circuit shown in FIG. 9C for generating the bank selection signal 226, includes a NAND gate 1105, an AND gate 1107, a D-latch circuit 1109 and two inverters 1106 and 118, connected as shown. The fourth read/write bank selection signal generating circuit shown in FIG. 9D for generating the bank selection signal 227, includes a NAND gate 1113, an AND gate 1115, a D-latch circuit 1116 and an inverter 1114, connected as shown.
In the prior art example shown in FIGS. 9A, 9B, 9C and 9D, the bank switching signal 248 for switching the bank number between two bank and four banks, is set to the logical high level. As mentioned above, the internal bank selection signals 208 and 209 are at the logical low level, and the bank activation signal 220 is at the logical high level. Therefore, in the first read/write bank selection signal generating circuit shown in FIG. 9A for the bank 700, an output of the AND gate 1102 is brought to the logical high level. On the other hand, in the third read/write bank selection signal generating circuit shown in FIG. 9C for the bank 702, although the bank activation signal 222 is at the logical high level, since an output of the NAND gate 1105 is at the logical low level, an output of the AND gate 1107 is at the logical low level. In the second and fourth read/write bank selection signal generating circuit shown in FIGS. 9B and 9D for the banks 701 and 703, at this time, an output of the AND gates 1111 and 1115 are at the logical low level, respectively. The output of these AND gates 1102, 1007, 1111 and 1115 are latched in the D-latches 1103, 1109, 1112 and 1116, respectively, in response to the internal read/write command signal 207, so that the read/write bank selection signal 224 of the logical high level and the read/write bank selection signals 225, 226 and 227 of the logical low level are outputted.
Furthermore, the address signal Ai, 244 supplied at the same time as the supplying of the read command, is latched in the clocked buffer circuit 216 in response to the internal clock signal 230, and further is latched in the D-latch 502 in response to the internal read/write command signal 207, so that the internal column address signal Yi, 246 is supplied to the memory cell array 101. At the timing T6 in the timing chart of FIG. 5, the column address value of the internal column address signal Yi, 246 corresponding to the address signal Ai, 244 is shown as a "COL1".
As shown in the bank structure diagram of FIG. 2, the read/write bank selection signal 224 and the internal column address signals Yi, 246 are supplied to the bank 700. As shown in the bank internal construction diagram of FIG. 3, the read/write bank selection signal 224 is supplied to the column switch driver 813 included in the column decode circuit 812. The internal column address signals Yi, 246 are also supplied to the column switch driver 813. If the read/write bank selection signal 224 is brought to the logical high level, the column switch driver 813 is activated, so that a signal (the output of the column switch driver 813) supplied to the column switch 814 selected by the column address value "COL1" is brought to the logical high level, with the result that the MOS transistors 815 and 817 acting as the reading switch are turned on. Therefore, data on the digit lines 809 and 810 are transferred through the MOS transistors 816 and 818 to the reading bus lines 819 and 820, respectively. The data amplifier circuit 821 is activated by the read/write bank selection signal 224 of the logical high level, so that the data on the reading bus lines 819 and 820 is amplified by the data amplifier circuit 821 and outputted through the input/output data line 704 to the external.
At a timing T7 in the timing chart of FIG. 5, the read command is supplied again, and the bank selection signals 200 and 201 are brought to the logical low level and the logical high level, respectively, so that the reading operation for another bank 702 is newly executed. The external active command signals including the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243, are supplied through the buffer circuits 212, 213, 214 and 215 to the command decode circuit 204, and decoded by the command decode circuit 204 to bring the internal read/write command signal 207 to the logical high level, again. Since the bank selection signals 200 and 201 are at the logical low level and at the logical high level, respectively, as mentioned above, the internal bank selection signals 208 and 209 outputted from the buffer circuits 210 and 211 are brought to the logical low level and the logical high level, respectively.
The internal read/write command signal 207 and the internal bank selection signals 208 and 209 are supplied to the read/write bank selection signal generating circuitry 901. In the third read/write bank selection signal generating circuit shown in FIG. 9C for the bank 702, since as mentioned above the internal bank selection signals 208 and 209 are at the logical low level and at the logical high level, respectively, and since the bank activation signal 222 is at the logical high level, the output of the AND gate 1107 is at the logical high level. On the other hand, in the first read/write bank selection signal generating circuit shown in FIG. 9A for the bank 700, although the bank activation signal 220 is at the logical high level, since the internal bank selection signal 209 is at the logical high level, the output of the AND gate 1102 is brought to the logical low level. In the second and fourth read/write bank selection signal generating circuit shown in FIGS. 9B and 9D for the banks 701 and 703, at this time, an output of the AND gates 1111 and 1115 are at the logical low level, respectively. The output of these AND gates 1102, 1007, 1111 and 1115 are latched in the D-latches 1103, 1109, 1112 and 1116, respectively, in response to the internal read/write command signal 207, so that the read/write bank selection signal 226 of the logical high level is outputted from the third read/write bank selection signal generating circuit for the bank 702, and and the read/write bank selection signals 224, 225 and 227 for the banks 700, 701 and 703 are maintained at the logical low level. At the same time, since the column address value "COL2" is supplied as the internal column address signals Yi, 246, data at the column address in the bank 702 and designated by the column address value "COL2" is read out in response to the read/write bank selection signal 226 of the logical high level.
What is labelled with "PRE" at a timing T10 in the timing chart of FIG. 5, is a precharge command, and is determined by a specific logical value combination of the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243, similarly to the other commands. This precharge command "PRE" corresponds to a rising of the RAS command signal 240 in a conventional DRAM, and has a function of fetching the bank selection signals 200 and 201, resetting the activation signals of the bank selected by the bank selection signals, and precharging the memory cell array.
At a timing T10 shown in FIG. 5, the external active command signals including the RAS command signal 240, the CAS command signal 241, the WE command signal 242 and the CS command signal 243, are supplied through the buffer circuits 212, 213, 214 and 215 to the command decode circuit 204 and decoded by the command decode circuit 204 so that the internal precharge signal 206 is brought to the logical high level. Since the internal bank activation signals 220 and 222 is at the logical high level at the timing T10, the banks 700 and 702 are in the activated condition. Accordingly, the banks to be precharged are the banks 700 and 702.
At the timing T10, both the bank selection signals 200 and 201 are set at the logical low level, so as to select the bank 700. These bank selection signals 200 and 201 are supplied through the clocked buffer circuits 210 and 211 as the internal bank selection signals 208 and 209 to the bank activation signal generating circuitry 900. Accordingly, at the timing T10, the internal bank selection signals 208 and 209 are both brought to the logical low level, so as to become consistent with the input logical value of the bank selection signals 200 and 201.
In the bank activation signal generating circuitry 900 shown in FIG. 6A, 6B, 6C and 6D, if the internal precharge command signal 206 of the logical high level is supplied, since both the internal bank selection signals 208 and 209 are at the logical low level, the output of the AND gate 1001 in the first bank activation signal generating circuit shown in FIG. 6A for the bank 700, is brought to the logical high level, and the output of the NOR gate 1004 is brought to the logical low level. On the other hand, since the internal activation command signal 205 is at the logical low level, the output of the AND gate 1000 is at the logical low level, so that the output of the NOR gate 1002 is brought to the logical high level. Thus, the output of the inverter 1003 is brought to the logical low level, with the result that the bank activation signal 220 for the bank 700 is brought to the logical low level. If the output of the NOR gate 1002 is brought to the logical high level as mentioned above, the output of the NOR gate 1004 is maintained at the logical low level, and therefore, the bank activation signal 220 for the bank 700 is maintained at the logical low level, regardless of the output of the AND gate 1001.
At a rising of the clock of a timing T11, the external active command signals are supplied again through the buffer circuits 212, 213, 214 and 215 to the command decode circuit 204, and decoded by the command decode circuit 204, so that the internal precharge signal 206 is brought to the logical low level. As a result, in the first bank activation signal generating circuit shown in FIG. 6A for the bank 700, the output of the AND gate 1001 is brought to the logical low level. Furthermore, in the internal construction of the banks 700-703 shown in FIG. 3, since the bank activation signal 220 has been brought to the logical low level, the word line driver 806 is deactivated so as to bring the word line 807 to the logical low level. In addition, the sense amplifier circuit 811 is deactivated in response to the bank activation signal 220 of the logical low level, so that the digit lines 809 and 810 are precharged.
At a timing T12 in the timing chart of FIG. 5, the precharge command is supplied again, and the bank selection signals 200 and 201 are set to the logical low level and the logical high level, respectively, for the purpose of precharging the bank 702. In this case, the internal precharge command signal 206 outputted from the command decode circuit 204 is brought the logical high level, again, and in accordance with the logical level of the bank selection signals 200 and 201, the internal bank selection signals 208 and 209 are brought to the logical low level and the logical high level, respectively.
In the bank activation signal generating circuit shown in FIG. 6C for the bank 702, if the internal precharge command signal 206 is brought to the logical high level again, since both the internal bank selection signals 208 and 209 are at the logical low level and the logical high level, respectively, the output of the AND gate 1014 is brought to the logical high level, and the output of the NOR gate 1017 is brought to the logical low level. On the other hand, since the internal activation command signal 205 is at the logical low level, the output of the AND gate 1013 is at the logical low level, so that the output of the NOR gate 1015 is brought to the logical high level. Thus, the output of the inverter 1016 is brought to the logical low level, with the result that the bank activation signal 222 for the bank 700 is brought to the logical low level. If the output of the NOR gate 1015 is brought to the logical high level, the output of the NOR gate 1017 is maintained at the logical low level, and therefore, the bank activation signal 222 is maintained at the logical low level, regardless of the output of the AND gate 1014.
At a rising of the clock of a timing T13, the external active command signals are supplied again through the buffer circuits 212, 213, 214 and 215 to the command decode circuit 204 and decoded by the command decode circuit 204 so that the internal precharge signal 206 is brought to the logical low level. As a result, the output of the AND gate 1014 is brought to the logical low level. Accordingly, in the bank 702, the sense amplifier circuit is deactivated in response to the bank activation signal 222 of the logical low level, so that the digit lines are precharged.
In the above description, the reading operation in the 4-bank structure has been explained. As mentioned above, in the case that the synchronous DRAM operates in the 4-bank structure, various operations including the activation of the memory bank, the read/write operation and the precharge operation is performed for a bank selected in accordance with the logical value combination of the bank selection signals 200 and 202 corresponding to two bits which make it possible to select one from four banks.
Next, the reading operation in a 2-bank structure will be explained. In the 2-bank structure, of the four banks each including the memory cell array and the control circuit therefore, the banks 700 and 702 are combined to constitute the same bank, and similarly, the banks 701 and 703 are combined to constitute the same bank. In the following description of the reading operation in the 2-bank structure, therefore, the banks 700, 701, 702 and 703 will be temporarily called "groups" 700, 701, 702 and 703, respectively, and it is considered that a first bank is constituted of the groups 700 and 702, and a second bank is constituted of the groups 701 and 703. Further, the bank selection is performed by only the logical value of the bank selection signal 200. Here, when the bank selection signal 200 is at the logical low level, the first bank constituted of the groups 700 and 702 is selected, and when the bank selection signal 200 is at the logical high level, the second bank constituted of the groups 701 and 703 is selected. The bank selection signal 201 used as the bank selection signal in the 4-bank structure as mentioned above, is handled as the most significant bit of the row address signal, and is used as a selection address for partially operating the bank in the first bank (groups 700 and 702) or in the second bank (groups 701 and 703) in the memory cell array 101 when it is activated. In the following reading operation of the 2-bank structure, therefore, this bank selection signal 201 will be temporarily called an "address signal 201", and correspondingly, the internal bank selection signal 209 will be temporarily called an "internal address signal 209".
When the first bank is activated, if the address signal 201 is at the logical low level, the group 700 of the memory cell array 101 is activated, and if the address signal 201 is at the logical high level, the group 702 of the memory cell array 101 is activated. When the second bank is activated, if the address signal 201 is at the logical low level, the group 701 of the memory cell array 101 is activated, and if the address signal 201 is at the logical high level, the group 703 of the memory cell array 101 is activated. In the read/write operation and in the precharge operation, an invalid input value is supplied to the address signal 201.
Referring to FIG. 10, there is shown a timing chart illustrating an operation of the synchronous DRAM in the 2-bank structure. At a timing T1 in the timing chart of FIG. 10, an active external command is supplied, and simultaneously, the address signals Ai, 244, the address signal 201 of the logical low level and the bank selection signal 200 of the logical low level are fetched, so that in the first bank constituted of the groups 700 and 702, the group 700 within the memory cell array 101 is activated. Furthermore, in response to the bank selection signal 200 of the logical low level and the address signal 201 of the logical low level, the internal bank selection signal 208 and the internal address signal 209 are both brought to the logical low level.
In the bank activation signal generating circuitry 900 having the internal construction shown in FIGS. 6A, 6B, 6C and 6D, the bank switching signal 248 of the logical low level is supplied, and on the other hand, the internal precharge command signal 206 is at the logical low level. Furthermore, it is assumed that all the bank activation signals 220, 221, 222 and 223 are at the logical low level.
In this condition, if the internal activation command signal 205 is brought to the logical high level, since the internal bank selection signal 208 is at the logical low level and the internal address signal 209 is at the logical low level, in the first bank activation signal generating circuit shown in FIG. 6A, the output of the AND gate 1000 is brought to the logical high level, and the output of the NOR gate 1002 is brought to the logical low level, so that the output of the inverter 1003 is brought to the logical high level, with the result that the bank activation signal 220 is brought to the logical high level. On the other hand, since the internal precharge command signal 206 is at the logical low level, the output of the AND gate 1001 is at the logical low level. Since the output of the NOR gate 1002 is at the logical low level, the output of the NOR gate 1004 is brought to the logical high level. Therefore, the output of the NOR gate 1002 is maintained at the logical low level, regardless of the output level of the AND gate 1000. Thus, the bank activation signal 220 is maintained at the logical high level.
At a rising of the clock signal in a timing T2 shown in FIG. 10, the internal activation command signal 205 is brought to the logical low level. In the first bank activation signal generating circuit shown in FIG. 6A for the group 700, accordingly, the output of the AND gate 1000 is brought to the logical low level at this time.
At the timing T1 in the timing chart of FIG. 10, since the row address value "ROW1" is supplied as the address signals Ai, 244, this row address value "ROW1" is transferred by the corresponding internal row address signals Xi, 245. The internal bank activation signal 220 of the logical high level is supplied to the group 700 included in the first bank. Thus, the word line designated by the row address value "ROW1" is selected, so that data of a corresponding memory cell is amplified by the sense amplifier circuit.
Incidentally, at a timing T6 in the timing chart of FIG. 10, the external read command is inputted, and the bank selection signal 200 of the logical low level is inputted, so that the reading operation is executed for the first bank. In this condition, the internal bank selection signal 208 is at the logical low level in accordance with the logical level of the bank selection signal 200.
In the read/write bank selection signal generating circuitry 901 having the internal construction as shown in FIGS. 9A, 9B, 9C and 9D, the bank switching signal 248 is at the logical low level and the internal precharge command signal 206 at the logical low level. Therefore, the output of all the NAND gates 1101, 1105, 1110 and 1113 receiving the internal address signal 209 are brought to the logical high level. Accordingly, the logical value of the internal address signal 209 corresponding to the external address signal 201 is not fetched as an effective value and therefore do not give any influence to an internal operation. Furthermore, since the internal bank selection signal 208 is at the logical low level, the output of the inverters 1104 and 1108 shown in FIGS. 9A and 9C are both at the logical high level. In addition, in the circuit shown in FIG. 9A, since the internal bank activation signal 220 is at the logical high level, the output of the AND gate 1102 is brought to the logical high level. On the other hand, in the circuit shown in FIG. 9C, since the internal bank activation signal 222 is at the logical low level, the output of the AND gate 1107 is at the logical low level. The output of the other AND gates 1111 and 1115 are the logical low level, since the internal bank selection signal 208 is at the logical low level.
The output of the AND gates 1102, 1107, 1111 and 1115 are latched in the D-latch circuits 1103, 1109, 1112 and 1116, respectively, in response to the internal read/write command signal 207. Thus, the internal read/write bank selection signal 224 of the logical high level and the internal read/write bank selection signals 226, 225 and 227 of the logical low level are outputted. In this situation, the column address value "COL1" of the internal column address signals Yi, 246 are simultaneously supplied as the address signals. Thus, in the group 700 of the first bank supplied with the internal read/write bank selection signal 224 of the logical high level, data is read out from the column address designated by the column address value "COL1".
At a timing T10 shown in FIG. 10, the external precharge command is inputted, and the bank selection signal 200 is brought to the logical low level for the purpose of precharging the first bank. The internal precharge command signal 206 is brought to the logical high level, and the internal bank selection signal 208 is brought to the logical low level in accordance with the logical value of the bank selection signal 200.
In the bank activation signal generating circuitry 900 having the internal construction shown in FIG. 6A, 6B, 6C and 6D, the bank switching signal 248 is at the logical low level, and the internal precharge command signal 206 is at the logical high level. Therefore, the output of all the NAND gates 1101, 1105, 1110 and 1113 receiving the internal address signal 209 are brought to the logical high level. Accordingly, the logical value of the internal address signal 209 corresponding to the external address signal 201 is not fetched as an effective value and therefore do not give any influence to an internal operation. Furthermore, since the internal bank selection signal 208 is at the logical low level, the output of the inverters 1005 and 1018 shown in FIGS. 6A and 6C are at the logical high level. However, in the first bank activation signal generating circuit shown in FIG. 6A, the output of the AND gate 1001 is brought to the logical high level since the bank activation signal 220 is at the logical high level and the internal precharge command signal 206 is at the logical high level, so that the output of the NOR gate 1004 is brought to the logical low level. On the other hand, in the third bank activation signal generating circuit shown in FIG. 6C, since the bank activation signal 222 is at the logical low level, the output of the AND gate 1014 is at the logical low level. An output of the other AND gates 1008 and 1020 remain at the logical low level, even if the internal precharge command signal 206 is brought to the logical high level.
In the first bank activation signal generating circuit shown in FIG. 6A, since the internal activation command signal 205 is at the logical low level, the output of the AND gate 1000 is at the logical low level. Thus, the output of the NOR gate 1002 is brought to the logical high level, so that the output of the inverter 1003 is brought to the logical low level, with the result that the bank activation signal 220 is brought to the logical low level. If the output of the NOR gate 1002 is brought to the logical high level as mentioned above, the output of the NOR gate 1004 is maintained at the logical low level, and therefore, the bank activation signal 220 is maintained at the logical low level, regardless of the output of the AND gate 1001.
At a rising of the clock of a timing T11 in FIG. 10, the internal precharge command signal 206 is brought to the logical low level. Accordingly, in the first bank activation signal generating circuit shown in FIG. 6A for the group 700 of the first bank, the output of the AND gate 1001 is brought to the logical low level. Furthermore, since the bank activation signal 220 has been brought to the logical low level, the word line driver 806 is deactivated so as to bring the word line 807 to the logical low level. In addition, the sense amplifier circuit 811 is deactivated in response to the bank activation signal 220 of the logical low level, so that the digit lines 809 and 810 are precharged.
Thus, the 2-bank structure operation has been described. In the case of the 2-bank structure operation, the activation of the memory bank, the read/write operation and the precharge operation are executed for the bank selected by the input logical value of only bank selection signal 200.
As mentioned above, when the prior art synchronous DRAM operates in the 4-bank structure, the read/write operation and the precharge operation are executed for one bank selected from the four banks by the input logical value of the bank selection signal of two bits (200 and 201). When the prior art synchronous DRAM operates in the 2-bank structure, the read/write operation and the precharge operation are executed for an activated group of the memory cell array, within one bank selected from the two banks by the input logical value of only bank selection signal 200. In this case, in the read/write operation and the precharge operation performed in the 2-bank structure, it is necessary to set the bank switching signal to the logical low level so as to invalidate the signal which is handled as the bank selection signal (201) in the 4-bank structure operation. However, this bank switching signal is fixed to either the logical high level or the logical low level in the product manufacturing process, so that the semiconductor memory manufactured as the synchronous DRAM is shipped with being classified into either the 2-bank structure semiconductor memory or the 4-bank structure semiconductor memory.
In a practical use, therefore, it is impossible to change the prior art synchronous DRAM from the 2-bank structure to the 4-bank structure and vice versa.